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Processors of the AMD EPYC 7002 Rome and 7003 Milan series expose more than eight memory controller channels that can be connected to a memory channel. Up to two DIMMs are supported per channel. To achieve the best possible overall performance, it is helpful to ensure a balanced allocation across all channels. This article presents frequently used DIMM configurations for these CPUs.
The following properties characterise processors of the AMD EPYC 7002/7003 series in terms of memory:
The highest possible memory bandwidth is particularly relevant in HPC environments. In other application areas, memory bandwidth has a lower impact on overall performance and depends on the specific workload. For example, tests show that applications can still achieve up to 90% of their potential performance with a memory bandwidth of about 35%. Configurations with fewer DIMMs reduce the maximum bandwidth but consume less energy and offer good expansion potential for the future.
Support references:
In single‑CPU systems with 8 DIMM slots, the following configurations are commonly used:
The following table shows possible DIMM configurations for a single‑CPU system with a mainboard featuring 16 DIMM slots (for example ASUS KRPA‑U16 mainboards / ASUS RS500A‑E11‑RS12U systems):
Officially supported speeds are DDR4‑3200 at 1 DPC and DDR4‑2933 at 2 DPC.
(See: [[https://www.tomshardware.com/news/amd-epyc-rome-sku-list-block-diagram,40115.html|AMD EPYC Rome SKU List and Block Diagram]] (tomshardware.com, 07.08.2019).)
In dual‑CPU systems with 16 DIMM slots (8 per CPU), typical balanced configurations are:
In dual‑CPU systems with 32 DIMM slots (16 per CPU), the following configurations are common:
